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John M Thendean

from Pleasanton, CA
Age ~46

John Thendean Phones & Addresses

  • 2703 Oregano Ct, Pleasanton, CA 94588 (925) 931-0556
  • 1435 Martin Luther King Jr Way #Y5, Berkeley, CA 94709 (510) 528-2862
  • Alameda, CA
  • Millbrae, CA
  • Stow, OH
  • Columbus, OH
  • Westport, CA

Industries

Semiconductors

Resumes

Resumes

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John Thendean

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Location:
San Francisco Bay Area
Industry:
Semiconductors

Publications

Us Patents

Digital Signal Processing Circuit Having Input Register Blocks

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US Patent:
7840627, Nov 23, 2010
Filed:
May 12, 2006
Appl. No.:
11/432823
Inventors:
James M. Simkins - Park City UT,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
Vasisht Mantra Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708490
Abstract:
An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Arithmetic Logic Unit Circuit

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US Patent:
7840630, Nov 23, 2010
Filed:
May 12, 2006
Appl. No.:
11/433333
Inventors:
Anna Wing Wah Wong - Santa Clara CA,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
James M. Simkins - Park City UT,
Vasisht Mantra Vadi - San Jose CA,
David P. Schultz - San Jose CA,
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708708
Abstract:
An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Digital Signal Processing Circuit Having A Pre-Adder Circuit

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US Patent:
7844653, Nov 30, 2010
Filed:
May 12, 2006
Appl. No.:
11/432848
Inventors:
James M. Simkins - Park City UT,
John M. Thendean - Berkeley CA,
Vasisht Mantra Vadi - San Jose CA,
Bernard J. New - Carmel Valley CA,
Jennifer Wong - Fremont CA,
Anna Wing Wah Wong - Santa Clara CA,
Alvin Y. Ching - Sunnyvale CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708490
Abstract:
A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Digital Signal Processing Circuit Having A Pattern Detector Circuit

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US Patent:
7849119, Dec 7, 2010
Filed:
May 12, 2006
Appl. No.:
11/432846
Inventors:
Vasisht Mantra Vadi - San Jose CA,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
James M. Simkins - Park City UT,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/04
US Classification:
708212
Abstract:
An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Architectural Floorplan For A Digital Signal Processing Circuit

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US Patent:
7853632, Dec 14, 2010
Filed:
May 12, 2006
Appl. No.:
11/433369
Inventors:
Alvin Y. Ching - Sunnyvale CA,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
James M. Simkins - Park City UT,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
Vasisht Mantra Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708232
Abstract:
A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Digital Signal Processing Circuit Having A Simd Circuit

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US Patent:
7853634, Dec 14, 2010
Filed:
May 12, 2006
Appl. No.:
11/433331
Inventors:
James M. Simkins - Park City UT,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
Vasisht Mantra Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708490
Abstract:
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Digital Signal Processing Circuit Having A Pattern Detector Circuit For Convergent Rounding

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US Patent:
7853636, Dec 14, 2010
Filed:
May 12, 2006
Appl. No.:
11/432847
Inventors:
Bernard J. New - Carmel Valley CA,
Jennifer Wong - Fremont CA,
James M. Simkins - Park City UT,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
Vasisht Mantra Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/499
US Classification:
708551
Abstract:
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Digital Signal Processing Circuit Having A Pattern Circuit For Determining Termination Conditions

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US Patent:
7860915, Dec 28, 2010
Filed:
May 12, 2006
Appl. No.:
11/433332
Inventors:
Vasisht Mantra Vadi - San Jose CA,
Jennifer Wong - Fremont CA,
Bernard J. New - Carmel Valley CA,
Alvin Y. Ching - Sunnyvale CA,
John M. Thendean - Berkeley CA,
Anna Wing Wah Wong - Santa Clara CA,
James M. Simkins - Park City UT,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/499
US Classification:
708552
Abstract:
A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.
John M Thendean from Pleasanton, CA, age ~46 Get Report